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| STS2DPF20V DUAL P-CHANNEL 20V - 0.14 - 2A SO-8 2.7V-DRIVE STripFETTM II POWER MOSFET PRELIMINARY DATA TYPE STS2DPF20V s s s s VDSS 20 V RDS(on) <0.20 (@4.5V) <0.25 (@2.7V) ID 2A TYPICAL RDS(on) = 0.14 (@4.5V) TYPICAL RDS(on) = 0.2 (@2.7V) ULTRA LOW THRESHOLD GATE DRIVE (2.7V) STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY SO-8 DESCRIPTION This Power MOSFET is the second generation of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s BATTERY MANAGMENT IN NOMADIC EQUIPMENT s POWER MANAGMENT IN CELLULAR PHONES MOSFET ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID IDM (q) PTOT Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Single Operation Drain Current (continuos) at TC = 100C Single Operation Drain Current (pulsed) Total Dissipation at TC = 25C Dual Operation Total Dissipation at TC = 25C Single Operation Value 20 20 12 2 1.26 8 1.6 2 Unit V V V A A A W W (q)Pulse width limited by safe operating area. Note: For the P-CHANNEL MOSFET actual polarity of Voltages and current has to be reversed August 2001 1/6 STS2DPF20V THERMAL DATA Rthj-amb Tstg Tj (*)Thermal Resistance Junction-ambient Single Operation Dual Operation Storage Temperature Junction-ambient Temperature (*) When Mounted on 0.5 in of 2 oz. Copper 62.5 78 -55 to 150 -55 to 150 C/W C/W C C MOSFET ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 12 V Min. 20 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 4.5 V, ID = 1 A VGS = 2.7 V, ID = 1 A Min. 0.6 0.14 0.20 0.20 0.25 Typ. Max. Unit V DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V, ID = 1.5 A VDS = 15V, f = 1 MHz, VGS = 0 Min. Typ. 4.5 315 87 17 Max. Unit S pF pF pF 2/6 STS2DPF20V ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 10 V, ID = 1.5A RG = 4.7 VGS = 4.5V (see test circuit, Figure 1) VDD = 10V, ID = 2 A, VGS = 4.5 V (see test circuit, Figure 2) Min. Typ. 38 30 3.8 0.34 0.8 4.8 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 10 V, ID = 1 A, RG = 4.7, VGS = 4.5 V (see test circuit, Figure 1) Min. Typ. 45 11 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 2 A, VGS = 0 ISD = 2 A, di/dt = 100A/s, VDD = 10 V, Tj = 150C (see test circuit, Figure 3) 15 7.5 1 Test Conditions Min. Typ. Max. 2 8 1.2 Unit A A V ns nC A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/6 STS2DPF20V Fig. 1: Switching Times Test Circuit For Resistive Load Fig. 2: Gate Charge test Circuit Fig. 3: Test Circuit For Diode Recovery Behaviour 4/6 STS2DPF20V SO-8 MECHANICAL DATA DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 0016023 5/6 STS2DPF20V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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